RESEARCH TRIANGLE PARK, USA: The ability to do more with less is about to become a reality as the chip industry is offered a way to increase performance without adding complexity.

Semiconductor Research Corp. (SRC), the world's leading university-research consortium for semiconductors and related technologies, announced achievement of unprecedented steps toward reaching the goal of building nodes in manufacturable volumes, using simpler design libraries than those currently employed by industry.

SRC's Focus Center Research Program (FCRP) and Carnegie-Mellon University have teamed to develop special design elements, called logic bricks, that have generated strong interest among the industry's leading chipmakers.

"Addressing the lithography challenges associated with scaling is of paramount importance to the semiconductor industry," said Shekhar Borkar, Intel Fellow. "The CMU team's breakthrough approach to design using logic bricks clearly shows that these challenges can be overcome by addressing printability concerns early in the design process. They have demonstrated in silicon that design with logic bricks does not imply a cost or performance overhead."

"It's becoming increasingly difficult to communicate complex layout sensitivities between fabricators and designers using conventional design rules," said Lars Liebmann, Distinguished Engineer, IBM Semiconductor Research and Development Center. "Maintaining aggressive technology scaling relies on comprehensive design-technology co-optimization that spans the entire logic-optimization to wafer-characterization flow. The SRC-funded research at CMU has demonstrated that communicating through a small number of predictably composable logic elements, or logic bricks, rather than conventional design rules, creates the bandwidth required to make such co-optimization possible."

Compared to current industry design techniques, researchers at CMU have demonstrated that a small number of well-chosen library design elements can produce competitive designs while removing lithographic issues that challenge other experimental state-of-art methods. Through extensive simulation, modeling and silicon validation, CMU's solution is in final testing by leading chipmakers for implementation in their design methodologies.

"We can't expect manufacturing to pull a miracle as they have done for past technology nodes. There has to be give and take among the design and manufacturing teams," said Larry Pileggi, professor of electrical engineering and computer science at Carnegie Mellon University. "However, based on industry response to this research, we're excited to bring more of what manufacturing can do into the design process in order to build superior designs."

The new technology can reduce transistor variability, increase effectiveness of resolution enhancement, improve yields and ultimately simplify design flows. Of particular interest is the reduced leakage with improved control across chip line-width variations.

In contrast to current industry approaches, CMU's logic bricks rely on simplified design rules and regular patterning. Rather than needing technological advances in manufacturing to accommodate design choices, the logic bricks best exploit how the chip is designed and how the patterns are most effectively printed. This progress allows use of existing lithography and manufacturing processes, enabling further advances that would otherwise be problematic for chip designers.

"This concept of building designs with logic bricks takes chip design to a new level that can extend advanced manufacturing without adding costs," said Betsy Weitzman, executive director of SRC's FCRP. "This breakthrough incorporates manufacturing capabilities as part of the library design phase of the chipmaking process. This will help us to maintain the needed balance between smarter and affordable architectures."

To date, CMU has designed an embedded processor and taped out several other blocks to test its technology against traditional standard-cell implementations. While these initial tape-outs at 65 and 45 nm demonstrated compelling results, CMU researchers believe that the full promise of the technology is about to be realized as commercial design methodologies are developed to fully accommodate regular logic bricks.

In validation of the technology, several integrated device manufacturers have endorsed vital progress from SRC's research with Carnegie-Mellon by collaboratively exploring the use of such design libraries for evaluation purposes down to the 32nm node.

Encouraged by its industry members to further prepare the technology for commercialization, SRC's Global Research Collaboration (GRC) is expanding the research of logic bricks in order for them to be applied to upcoming nodes.