BANGALORE, INDIA: The semiconductor industry is maturing.  Since 2000 the industry’s annual growth rate has experienced extreme highs and lows.

Though semi industry revenue growth will be low in 2007, the good news is that growth rates are smoothing out as costly fabs demand consistent production.  Wireless communications, computers, and consumer products continue to be the growth drivers for semiconductors.

A couple of the semiconductor technology trends driving electronic design and product development are:

* More designs at advanced nodes — Beginning this year, designs at 90nm will outnumber those at 130nm. Meanwhile, 65nm is design activity is ramping up and advanced designs are targeting 45nm.

* Growth in transistor count and logic — Not only are transistor counts increasing according to Moore’s law, but those transistors are being used to create more functionality – and therefore more complexity – on a single chip, not just add memory to existing designs.

A related trend is that the amount of chip production outsourced to foundries continues to grow, with many Integrated Device Manufacturers (IDMs) moving to a “fab-lite” strategy for advanced nodes. This is happening as design is becoming a greater product differentiation than production.

All of these trends create two kinds of challenges for chip design:  1) manufacturability at advanced process nodes like 90nm and below, and 2) increased complexity and scale of chip design of system-on-chip.

Design solutions today must address these challenges and also increase team productivity and schedule predictability. To accomplish this, Cadence is focused on a holistic approach to the design flow.  The Cadence Low-Power Solution and the Encounter Timing System are good examples of this holistic approach addressing the challenges of escalating scale and complexity. 

The same holistic approach is shown in Cadence’s approach to manufacturability, which is to integrate design for manufacturability (DFM) into all aspects of the design flow, rather than just apply DFM techniques as a post-design step.

Cadence has recently launched the following solutions that compliment the company’s current breadth and depth of technology and help enable SMART TO FINISH design:

* Encounter Timing System with statistical static timing analysis (SSTA).
* The SoC Functional Verification Kit.
* Open Verification Methodology program jointly developed by Cadence and Mentor Graphics.
* Cadence VCAD or “virtual CAD” to help you implement, improve, and maintain your design team.
* Model-based DFM technology integrated into the design flow, including litho modeling capability from Cadence’s recent acquisition of Clear Shape. 

Although many recent Cadence developments are driven by requirements of advanced nodes like 65nm and 45nm, chip designers at all nodes benefit from the holistic approach because it improves productivity, quality, and predictability.

The author is the president and CEO, Cadence Design Systems Inc. He was in India for the CDNLive event.