PUNE, INDIA: Accel IT Academy, Pune is conducting a free VLSI seminar on 'Verification Engineering' on 11 July 2008 at its FC Road office.

The company has recently acquired license for conducting VLSI design engineering using Cadence tools.

What is verification all about?
Verification in Chip Design is the most vital part of the complete design process. Unless a design is verified, we cannot be 100 percent sure that the design will work correctly. In present times, the chip design process has become very much complex, and billions of gates are added on one small chip.

Even one bug in design can cost billions or trillions of bucks. So, you can well imagine just how important verification is!

As continuous research is making it possible to go for the smallest form size, the process of verification for such designs has become the most challenging part in any design cycle.

The first and major part of the verification is functional verification. Functional verification is done to check the correctness of design. There are lots of techniques and methods, which have evolved over time. Hardware verification languages like OpenVera, Specman e and System C are available for formal verification.

The most effective languages among these is the e language, which was specially developed for complete formal verification, effective for the main areas of verification: data generation, checking and coverage.

Therefore, hardware engineers now need to know how much has to be generated and checked? How much has been covered? Therefore, they can have the complete solution for formal verification, whatever the complexity of any design.

The only tool available in market for e language is the Specman Elite from Verisity, which is now owned by Cadence.

Those interested to register for the seminar, contact manoji@accelitacademy.com.